High speed computer systems often utilize burst mode clocked static random access memories (SRAMs) as secondary data cache memory. A burst mode SRAM is a synchronous SRAM device which has a burst mode and is therefore used as an integral component in cache memory systems such as the Intel 486 or the Motorola family of microprocessors. The burst SRAM device has a burst counter which controls the burst of data produced by the burst mode. The burst mode address sequence of a burst SRAM device is advantageous for fast cache-fill operations. At each clock cycle, the cache memory chip must decide, based on the current state of the control inputs, whether to initiate a burst count address based on the internal address state of the previous clock state or to load in the current external address presented at the memory chip address inputs. In addition to burst SRAM technology, there are many other applications where it is necessary to retain old data and therefore be able to know what a previous state of data was. For instance, any number of logic applications which employ decision trees commonly make a decision or take a branch of a decision tree based upon the logic state of old data.
In high speed clocked memory design, the overall memory access delay is often enhanced by using pre-charged data path techniques that increase effective gate fanout in the implementation of the address decode path and also minimize access delays thereby increasing the speed of the memory device. This approach requires that the address decode path be reset (or pre-charged) to a given logic state, usually inactive, prior to the address decode path master clock strobe. Address inputs to the pre-charged address decode path must also be valid prior to the active strobe. When the decode path strobe goes active, the input data (or address) is allowed to enter the pre-charged decode path and ripple through to the output stage. When the decode path strobe goes inactive, the data or address is usually latched in the output stage and the decode path is once more pre-charged to the inactive state.
While the pre-charged data path techniques have been successfully used for high speed clocked memory design, they have never been employed in applications where it is necessary to retain old data in order to know the previous state of the data, such as is the case with burst SRAM technology. Burst SRAM memory design present difficulties in using pre-charged data path techniques because of the special considerations attendant with the necessity of having the previous burst sequence state available and selectable if so required by the burst SRAM control input signals. Thus, the advantages of the pre-charged data path techniques such as increased gate fanout in the address decode path and increased memory access have to date not been available on burst SRAM memories. There is an unmet need in the art to be able to effectively use pre-charged decode path techniques in technologies where it is necessary to retain old data for possible future use, such as clocked burst SRAM technology.